Changeset 3 for gpxe_study
- Timestamp:
- Feb 13, 2008, 5:15:44 PM (17 years ago)
- File:
-
- 1 edited
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gpxe_study/kernel_2.6.20_src/sis900.h (modified) (9 diffs)
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gpxe_study/kernel_2.6.20_src/sis900.h
r2 r3 3 3 * References: 4 4 * SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support, 5 * 5 * preliminary Rev. 1.0 Jan. 14, 1998 6 6 * SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support, 7 * 7 * preliminary Rev. 1.0 Nov. 10, 1998 8 8 * SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution, 9 * 9 * preliminary Rev. 1.0 Jan. 18, 1998 10 10 * http://www.sis.com.tw/support/databook.htm 11 11 */ … … 20 20 /* Symbolic offsets to registers. */ 21 21 enum sis900_registers { 22 cr=0x0, //Command Register 23 cfg=0x4, //Configuration Register 24 mear=0x8, //EEPROM Access Register 25 ptscr=0xc, //PCI Test Control Register 26 isr=0x10, //Interrupt Status Register 27 imr=0x14, //Interrupt Mask Register 28 ier=0x18, //Interrupt Enable Register 29 epar=0x18, //Enhanced PHY Access Register 30 txdp=0x20, //Transmit Descriptor Pointer Register 31 txcfg=0x24, //Transmit Configuration Register32 rxdp=0x30, //Receive Descriptor Pointer Register33 rxcfg=0x34, //Receive Configuration Register34 flctrl=0x38, //Flow Control Register35 rxlen=0x3c, //Receive Packet Length Register36 rfcr=0x48, //Receive Filter Control Register37 rfdr=0x4C, //Receive Filter Data Register38 pmctrl=0xB0, //Power Management Control Register39 pmer=0xB4 //Power Management Wake-up Event Register22 cr=0x0, /* Command Register */ 23 cfg=0x4, /* Configuration Register */ 24 mear=0x8, /* EEPROM Access Register */ 25 ptscr=0xc, /* PCI Test Control Register */ 26 isr=0x10, /* Interrupt Status Register */ 27 imr=0x14, /* Interrupt Mask Register */ 28 ier=0x18, /* Interrupt Enable Register */ 29 epar=0x18, /* Enhanced PHY Access Register */ 30 txdp=0x20, /* Transmit Descriptor Pointer Register */ 31 txcfg=0x24, /* Transmit Configuration Register */ 32 rxdp=0x30, /* Receive Descriptor Pointer Register */ 33 rxcfg=0x34, /* Receive Configuration Register */ 34 flctrl=0x38, /* Flow Control Register */ 35 rxlen=0x3c, /* Receive Packet Length Register */ 36 rfcr=0x48, /* Receive Filter Control Register */ 37 rfdr=0x4C, /* Receive Filter Data Register */ 38 pmctrl=0xB0, /* Power Management Control Register */ 39 pmer=0xB4 /* Power Management Wake-up Event Register */ 40 40 }; 41 41 42 42 /* Symbolic names for bits in various registers */ 43 43 enum sis900_command_register_bits { 44 RELOAD = 0x00000400, ACCESSMODE = 0x00000200,/* ET */ 45 RESET = 0x00000100, SWI = 0x00000080, RxRESET = 0x00000020, 46 TxRESET = 0x00000010, RxDIS = 0x00000008, RxENA = 0x00000004, 47 TxDIS = 0x00000002, TxENA = 0x00000001 44 RELOAD = 0x00000400, 45 ACCESSMODE = 0x00000200, 46 RESET = 0x00000100, 47 SWI = 0x00000080, 48 RxRESET = 0x00000020, 49 TxRESET = 0x00000010, 50 RxDIS = 0x00000008, 51 RxENA = 0x00000004, 52 TxDIS = 0x00000002, 53 TxENA = 0x00000001 48 54 }; 49 55 50 56 enum sis900_configuration_register_bits { 51 DESCRFMT = 0x00000100 /* 7016 specific */, REQALG = 0x00000080, 52 SB = 0x00000040, POW = 0x00000020, EXD = 0x00000010, 53 PESEL = 0x00000008, LPM = 0x00000004, BEM = 0x00000001, 54 /* 635 & 900B Specific */ 55 RND_CNT = 0x00000400, FAIR_BACKOFF = 0x00000200, 56 EDB_MASTER_EN = 0x00002000 57 DESCRFMT = 0x00000100, /* 7016 specific */ 58 REQALG = 0x00000080, 59 SB = 0x00000040, 60 POW = 0x00000020, 61 EXD = 0x00000010, 62 PESEL = 0x00000008, 63 LPM = 0x00000004, 64 BEM = 0x00000001, 65 RND_CNT = 0x00000400, 66 FAIR_BACKOFF = 0x00000200, 67 EDB_MASTER_EN = 0x00002000 57 68 }; 58 69 59 70 enum sis900_eeprom_access_reigster_bits { 60 MDC = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010, /* 7016 specific */ 61 EECS = 0x00000008, EECLK = 0x00000004, EEDO = 0x00000002, 62 EEDI = 0x00000001 71 MDC = 0x00000040, 72 MDDIR = 0x00000020, 73 MDIO = 0x00000010, /* 7016 specific */ 74 EECS = 0x00000008, 75 EECLK = 0x00000004, 76 EEDO = 0x00000002, 77 EEDI = 0x00000001 63 78 }; 64 79 65 80 enum sis900_interrupt_register_bits { 66 WKEVT = 0x10000000, TxPAUSEEND = 0x08000000, TxPAUSE = 0x04000000, 67 TxRCMP = 0x02000000, RxRCMP = 0x01000000, DPERR = 0x00800000, 68 SSERR = 0x00400000, RMABT = 0x00200000, RTABT = 0x00100000, 69 RxSOVR = 0x00010000, HIBERR = 0x00008000, SWINT = 0x00001000, 70 MIBINT = 0x00000800, TxURN = 0x00000400, TxIDLE = 0x00000200, 71 TxERR = 0x00000100, TxDESC = 0x00000080, TxOK = 0x00000040, 72 RxORN = 0x00000020, RxIDLE = 0x00000010, RxEARLY = 0x00000008, 73 RxERR = 0x00000004, RxDESC = 0x00000002, RxOK = 0x00000001 81 WKEVT = 0x10000000, 82 TxPAUSEEND = 0x08000000, 83 TxPAUSE = 0x04000000, 84 TxRCMP = 0x02000000, 85 RxRCMP = 0x01000000, 86 DPERR = 0x00800000, 87 SSERR = 0x00400000, 88 RMABT = 0x00200000, 89 RTABT = 0x00100000, 90 RxSOVR = 0x00010000, 91 HIBERR = 0x00008000, 92 SWINT = 0x00001000, 93 MIBINT = 0x00000800, 94 TxURN = 0x00000400, 95 TxIDLE = 0x00000200, 96 TxERR = 0x00000100, 97 TxDESC = 0x00000080, 98 TxOK = 0x00000040, 99 RxORN = 0x00000020, 100 RxIDLE = 0x00000010, 101 RxEARLY = 0x00000008, 102 RxERR = 0x00000004, 103 RxDESC = 0x00000002, 104 RxOK = 0x00000001 74 105 }; 75 106 76 107 enum sis900_interrupt_enable_reigster_bits { 77 108 IE = 0x00000001 78 109 }; 79 110 80 111 /* maximum dma burst for transmission and receive */ 81 #define MAX_DMA_RANGE 7 /* actually 0 means MAXIMUM !! */ 82 #define TxMXDMA_shift 20 83 #define RxMXDMA_shift 20 112 #define MAX_DMA_RANGE 7 /* actually 0 means MAXIMUM !! */ 113 #define TxMXDMA_shift 20 114 #define RxMXDMA_shift 20 115 #define TX_DMA_BURST 0 116 #define RX_DMA_BURST 0 84 117 85 118 enum sis900_tx_rx_dma{ 86 DMA_BURST_512 = 0,DMA_BURST_64 = 5119 DMA_BURST_512 = 0, DMA_BURST_64 = 5 87 120 }; 88 121 89 122 /* transmit FIFO thresholds */ 90 #define TX_FILL_THRESH 16/* 1/4 FIFO size */91 #define TxFILLT_shift 92 #define TxDRNT_shift 93 #define TxDRNT_100 48/* 3/4 FIFO size */94 #define TxDRNT_10 16/* 1/2 FIFO size */123 #define TX_FILL_THRESH 16 /* 1/4 FIFO size */ 124 #define TxFILLT_shift 8 125 #define TxDRNT_shift 0 126 #define TxDRNT_100 48 /* 3/4 FIFO size */ 127 #define TxDRNT_10 16 /* 1/2 FIFO size */ 95 128 96 129 enum sis900_transmit_config_register_bits { 97 TxCSI = 0x80000000, TxHBI = 0x40000000, TxMLB = 0x20000000, 98 TxATP = 0x10000000, TxIFG = 0x0C000000, TxFILLT = 0x00003F00, 99 TxDRNT = 0x0000003F 130 TxCSI = 0x80000000, 131 TxHBI = 0x40000000, 132 TxMLB = 0x20000000, 133 TxATP = 0x10000000, 134 TxIFG = 0x0C000000, 135 TxFILLT = 0x00003F00, 136 TxDRNT = 0x0000003F 100 137 }; 101 138 102 139 /* recevie FIFO thresholds */ 103 140 #define RxDRNT_shift 1 104 #define RxDRNT_100 16/* 1/2 FIFO size */105 #define RxDRNT_10 24/* 3/4 FIFO size */141 #define RxDRNT_100 16 /* 1/2 FIFO size */ 142 #define RxDRNT_10 24 /* 3/4 FIFO size */ 106 143 107 144 enum sis900_reveive_config_register_bits { 108 RxAEP = 0x80000000, RxARP = 0x40000000, RxATX = 0x10000000, 109 RxAJAB = 0x08000000, RxDRNT = 0x0000007F 145 RxAEP = 0x80000000, 146 RxARP = 0x40000000, 147 RxATX = 0x10000000, 148 RxAJAB = 0x08000000, 149 RxDRNT = 0x0000007F 110 150 }; 111 151 … … 114 154 115 155 enum sis900_receive_filter_control_register_bits { 116 RFEN = 0x80000000, RFAAB = 0x40000000, RFAAM = 0x20000000, 117 RFAAP = 0x10000000, RFPromiscuous = (RFAAB|RFAAM|RFAAP) 156 RFEN = 0x80000000, 157 RFAAB = 0x40000000, 158 RFAAM = 0x20000000, 159 RFAAP = 0x10000000, 160 RFPromiscuous = (RFAAB|RFAAM|RFAAP) 118 161 }; 119 162 120 163 enum sis900_reveive_filter_data_mask { 121 164 RFDAT = 0x0000FFFF 122 165 }; 123 166 124 167 /* EEPROM Addresses */ 125 168 enum sis900_eeprom_address { 126 EEPROMSignature = 0x00, EEPROMVendorID = 0x02, EEPROMDeviceID = 0x03, 127 EEPROMMACAddr = 0x08, EEPROMChecksum = 0x0b 169 EEPROMSignature = 0x00, 170 EEPROMVendorID = 0x02, 171 EEPROMDeviceID = 0x03, 172 EEPROMMACAddr = 0x08, 173 EEPROMChecksum = 0x0b 128 174 }; 129 175 130 176 /* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */ 131 177 enum sis900_eeprom_command { 132 EEread = 0x0180, EEwrite = 0x0140, EEerase = 0x01C0, 133 EEwriteEnable = 0x0130, EEwriteDisable = 0x0100, 134 EEeraseAll = 0x0120, EEwriteAll = 0x0110, 135 EEaddrMask = 0x013F, EEcmdShift = 16 178 EEread = 0x0180, 179 EEwrite = 0x0140, 180 EEerase = 0x01C0, 181 EEwriteEnable = 0x0130, 182 EEwriteDisable = 0x0100, 183 EEeraseAll = 0x0120, 184 EEwriteAll = 0x0110, 185 EEaddrMask = 0x013F, 186 EEcmdShift = 16 136 187 }; 137 188 … … 195 246 /* Buffer Descriptor Status*/ 196 247 enum sis900_buffer_status { 197 OWN = 0x80000000, MORE = 0x40000000, INTR = 0x20000000, 198 SUPCRC = 0x10000000, INCCRC = 0x10000000, 199 OK = 0x08000000, DSIZE = 0x00000FFF 248 OWN = 0x80000000, 249 MORE = 0x40000000, 250 INTR = 0x20000000, 251 SUPCRC = 0x10000000, 252 INCCRC = 0x10000000, 253 OK = 0x08000000, 254 DSIZE = 0x00000FFF 200 255 }; 201 256 /* Status for TX Buffers */ 202 257 enum sis900_tx_buffer_status { 203 ABORT = 0x04000000, UNDERRUN = 0x02000000, NOCARRIER = 0x01000000, 204 DEFERD = 0x00800000, EXCDEFER = 0x00400000, OWCOLL = 0x00200000, 205 EXCCOLL = 0x00100000, COLCNT = 0x000F0000 258 ABORT = 0x04000000, 259 UNDERRUN = 0x02000000, 260 NOCARRIER = 0x01000000, 261 DEFERD = 0x00800000, 262 EXCDEFER = 0x00400000, 263 OWCOLL = 0x00200000, 264 EXCCOLL = 0x00100000, 265 COLCNT = 0x000F0000 206 266 }; 207 267 208 268 enum sis900_rx_bufer_status { 209 OVERRUN = 0x02000000, DEST = 0x00800000, BCAST = 0x01800000, 210 MCAST = 0x01000000, UNIMATCH = 0x00800000, TOOLONG = 0x00400000, 211 RUNT = 0x00200000, RXISERR = 0x00100000, CRCERR = 0x00080000, 212 FAERR = 0x00040000, LOOPBK = 0x00020000, RXCOL = 0x00010000 269 OVERRUN = 0x02000000, 270 DEST = 0x00800000, 271 BCAST = 0x01800000, 272 MCAST = 0x01000000, 273 UNIMATCH = 0x00800000, 274 TOOLONG = 0x00400000, 275 RUNT = 0x00200000, 276 RXISERR = 0x00100000, 277 CRCERR = 0x00080000, 278 FAERR = 0x00040000, 279 LOOPBK = 0x00020000, 280 RXCOL = 0x00010000 213 281 }; 214 282 215 283 /* MII register offsets */ 216 284 enum mii_registers { 217 MII_CONTROL = 0x0000, MII_STATUS = 0x0001, MII_PHY_ID0 = 0x0002, 218 MII_PHY_ID1 = 0x0003, MII_ANADV = 0x0004, MII_ANLPAR = 0x0005, 219 MII_ANEXT = 0x0006 285 MII_CONTROL = 0x0000, 286 MII_STATUS = 0x0001, 287 MII_PHY_ID0 = 0x0002, 288 MII_PHY_ID1 = 0x0003, 289 MII_ANADV = 0x0004, 290 MII_ANLPAR = 0x0005, 291 MII_ANEXT = 0x0006 220 292 }; 221 293 222 294 /* mii registers specific to SiS 900 */ 223 295 enum sis_mii_registers { 224 MII_CONFIG1 = 0x0010, MII_CONFIG2 = 0x0011, MII_STSOUT = 0x0012, 225 MII_MASK = 0x0013, MII_RESV = 0x0014 296 MII_CONFIG1 = 0x0010, 297 MII_CONFIG2 = 0x0011, 298 MII_STSOUT = 0x0012, 299 MII_MASK = 0x0013, 300 MII_RESV = 0x0014 301 }; 302 303 /* mii registers specific to AMD 79C901 */ 304 enum amd_mii_registers { 305 MII_STATUS_SUMMARY = 0x0018 226 306 }; 227 307 … … 232 312 }; 233 313 234 /* mii registers specific to AMD 79C901 */ 235 enum amd_mii_registers { 236 MII_STATUS_SUMMARY = 0x0018 237 }; 314 238 315 239 316 /* MII Control register bit definitions. */ 240 317 enum mii_control_register_bits { 241 MII_CNTL_FDX = 0x0100, MII_CNTL_RST_AUTO = 0x0200, 242 MII_CNTL_ISOLATE = 0x0400, MII_CNTL_PWRDWN = 0x0800, 243 MII_CNTL_AUTO = 0x1000, MII_CNTL_SPEED = 0x2000, 244 MII_CNTL_LPBK = 0x4000, MII_CNTL_RESET = 0x8000 318 MII_CNTL_FDX = 0x0100, 319 MII_CNTL_RST_AUTO = 0x0200, 320 MII_CNTL_ISOLATE = 0x0400, 321 MII_CNTL_PWRDWN = 0x0800, 322 MII_CNTL_AUTO = 0x1000, 323 MII_CNTL_SPEED = 0x2000, 324 MII_CNTL_LPBK = 0x4000, 325 MII_CNTL_RESET = 0x8000 245 326 }; 246 327 247 328 /* MII Status register bit */ 248 329 enum mii_status_register_bits { 249 MII_STAT_EXT = 0x0001, MII_STAT_JAB = 0x0002, 250 MII_STAT_LINK = 0x0004, MII_STAT_CAN_AUTO = 0x0008, 251 MII_STAT_FAULT = 0x0010, MII_STAT_AUTO_DONE = 0x0020, 252 MII_STAT_CAN_T = 0x0800, MII_STAT_CAN_T_FDX = 0x1000, 253 MII_STAT_CAN_TX = 0x2000, MII_STAT_CAN_TX_FDX = 0x4000, 254 MII_STAT_CAN_T4 = 0x8000 255 }; 256 257 #define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */ 258 #define MII_ID1_MODEL 0x03F0 /* model number */ 259 #define MII_ID1_REV 0x000F /* model number */ 330 MII_STAT_EXT = 0x0001, 331 MII_STAT_JAB = 0x0002, 332 MII_STAT_LINK = 0x0004, 333 MII_STAT_CAN_AUTO = 0x0008, 334 MII_STAT_FAULT = 0x0010, 335 MII_STAT_AUTO_DONE = 0x0020, 336 MII_STAT_CAN_T = 0x0800, 337 MII_STAT_CAN_T_FDX = 0x1000, 338 MII_STAT_CAN_TX = 0x2000, 339 MII_STAT_CAN_TX_FDX = 0x4000, 340 MII_STAT_CAN_T4 = 0x8000 341 }; 342 343 #define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */ 344 #define MII_ID1_MODEL 0x03F0 /* model number */ 345 #define MII_ID1_REV 0x000F /* model number */ 260 346 261 347 /* MII NWAY Register Bits ... … … 263 349 ANLPAR (Auto-Negotiation Link Partner) registers */ 264 350 enum mii_nway_register_bits { 265 MII_NWAY_NODE_SEL = 0x001f, MII_NWAY_CSMA_CD = 0x0001, 266 MII_NWAY_T = 0x0020, MII_NWAY_T_FDX = 0x0040, 267 MII_NWAY_TX = 0x0080, MII_NWAY_TX_FDX = 0x0100, 268 MII_NWAY_T4 = 0x0200, MII_NWAY_PAUSE = 0x0400, 269 MII_NWAY_RF = 0x2000, MII_NWAY_ACK = 0x4000, 270 MII_NWAY_NP = 0x8000 351 MII_NWAY_NODE_SEL = 0x001f, 352 MII_NWAY_CSMA_CD = 0x0001, 353 MII_NWAY_T = 0x0020, 354 MII_NWAY_T_FDX = 0x0040, 355 MII_NWAY_TX = 0x0080, 356 MII_NWAY_TX_FDX = 0x0100, 357 MII_NWAY_T4 = 0x0200, 358 MII_NWAY_PAUSE = 0x0400, 359 MII_NWAY_RF = 0x2000, 360 MII_NWAY_ACK = 0x4000, 361 MII_NWAY_NP = 0x8000 271 362 }; 272 363 273 364 enum mii_stsout_register_bits { 274 MII_STSOUT_LINK_FAIL = 0x4000, 275 MII_STSOUT_SPD = 0x0080, MII_STSOUT_DPLX = 0x0040 365 MII_STSOUT_LINK_FAIL = 0x4000, 366 MII_STSOUT_SPD = 0x0080, 367 MII_STSOUT_DPLX = 0x0040 276 368 }; 277 369 … … 282 374 283 375 enum mii_stssum_register_bits { 284 MII_STSSUM_LINK = 0x0008, MII_STSSUM_DPLX = 0x0004, 285 MII_STSSUM_AUTO = 0x0002, MII_STSSUM_SPD = 0x0001 376 MII_STSSUM_LINK = 0x0008, 377 MII_STSSUM_DPLX = 0x0004, 378 MII_STSSUM_AUTO = 0x0002, 379 MII_STSSUM_SPD = 0x0001 286 380 }; 287 381 … … 289 383 SIS630A_900_REV = 0x80, SIS630E_900_REV = 0x81, 290 384 SIS630S_900_REV = 0x82, SIS630EA1_900_REV = 0x83, 291 SIS630ET_900_REV = 0x84, 385 SIS630ET_900_REV = 0x84, SIS635A_900_REV = 0x90, 292 386 SIS96x_900_REV = 0X91, SIS900B_900_REV = 0x03 293 387 }; … … 302 396 #define FDX_CAPABLE_FULL_SELECTED 2 303 397 304 #define HW_SPEED_UNCONFIG 305 #define HW_SPEED_HOME 306 #define HW_SPEED_10_MBPS 307 #define HW_SPEED_100_MBPS 308 #define HW_SPEED_DEFAULT 309 310 #define CRC_SIZE 311 #define MAC_HEADER_SIZE 398 #define HW_SPEED_UNCONFIG 0 399 #define HW_SPEED_HOME 1 400 #define HW_SPEED_10_MBPS 10 401 #define HW_SPEED_100_MBPS 100 402 #define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS) 403 404 #define CRC_SIZE 4 405 #define MAC_HEADER_SIZE 14 312 406 313 407 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
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